/*
 * Copyright (c) 2021 MediaTek Inc.
 *
 * Use of this source code is governed by a MIT-style
 * license that can be found in the LICENSE file or at
 * https://opensource.org/licenses/MIT
 */

#pragma once

#include <platform/addressmap.h>
#include <platform/reg.h>

/**************************************
 * SRAMROM
 **************************************/
#define SECURITY_AO                 (IO_BASE + 0x0001A000)

#define SRAMROM_SEC_CTRL        (SECURITY_AO + 0x010)
#define SRAMROM_SEC_CTRL2       (SECURITY_AO + 0x018)
#define SRAMROM_SEC_CTRL5       (SECURITY_AO + 0x024)
#define SRAMROM_SEC_CTRL6       (SECURITY_AO + 0x028)

#define SRAMROM_SEC_ADDR        (SECURITY_AO + 0x050)
#define SRAMROM_SEC_ADDR1       (SECURITY_AO + 0x054)
#define SRAMROM_SEC_ADDR2       (SECURITY_AO + 0x058)

#define SRAMROM_DM_REMAP0       (SECURITY_AO + 0x110)
#define SRAMROM_DM_REMAP1       (SECURITY_AO + 0x114)

#define SRAMROM_SEC_ADDR_MASK        (0x0003FC00)

#define SRAMROM_SEC_ADDR_SEC0_SEC_EN       (28)
#define SRAMROM_SEC_ADDR_SEC1_SEC_EN       (29)
#define SRAMROM_SEC_ADDR_SEC2_SEC_EN       (30)
#define SRAMROM_SEC_ADDR_SEC3_SEC_EN       (31)

//SEC0 means region 0, SEC3 means region 3
#define SRAMROM_SEC_CTRL_SEC0_DOM0_SHIFT   (0)
#define SRAMROM_SEC_CTRL_SEC0_DOM1_SHIFT   (3)
#define SRAMROM_SEC_CTRL_SEC0_DOM2_SHIFT   (6)
#define SRAMROM_SEC_CTRL_SEC0_DOM3_SHIFT   (9)
#define SRAMROM_SEC_CTRL_SEC1_DOM0_SHIFT   (16)
#define SRAMROM_SEC_CTRL_SEC1_DOM1_SHIFT   (19)
#define SRAMROM_SEC_CTRL_SEC1_DOM2_SHIFT   (22)
#define SRAMROM_SEC_CTRL_SEC1_DOM3_SHIFT   (25)

#define SRAMROM_SEC_CTRL2_SEC0_DOM4_SHIFT  (0)
#define SRAMROM_SEC_CTRL2_SEC0_DOM5_SHIFT  (3)
#define SRAMROM_SEC_CTRL2_SEC0_DOM6_SHIFT  (6)
#define SRAMROM_SEC_CTRL2_SEC0_DOM7_SHIFT  (9)
#define SRAMROM_SEC_CTRL2_SEC1_DOM4_SHIFT  (16)
#define SRAMROM_SEC_CTRL2_SEC1_DOM5_SHIFT  (19)
#define SRAMROM_SEC_CTRL2_SEC1_DOM6_SHIFT  (22)
#define SRAMROM_SEC_CTRL2_SEC1_DOM7_SHIFT  (25)

#define SRAMROM_SEC_CTRL5_SEC2_DOM0_SHIFT  (0)
#define SRAMROM_SEC_CTRL5_SEC2_DOM1_SHIFT  (3)
#define SRAMROM_SEC_CTRL5_SEC2_DOM2_SHIFT  (6)
#define SRAMROM_SEC_CTRL5_SEC2_DOM3_SHIFT  (9)
#define SRAMROM_SEC_CTRL5_SEC3_DOM0_SHIFT  (16)
#define SRAMROM_SEC_CTRL5_SEC3_DOM1_SHIFT  (19)
#define SRAMROM_SEC_CTRL5_SEC3_DOM2_SHIFT  (22)
#define SRAMROM_SEC_CTRL5_SEC3_DOM3_SHIFT  (25)

#define SRAMROM_SEC_CTRL6_SEC2_DOM4_SHIFT  (0)
#define SRAMROM_SEC_CTRL6_SEC2_DOM5_SHIFT  (3)
#define SRAMROM_SEC_CTRL6_SEC2_DOM6_SHIFT  (6)
#define SRAMROM_SEC_CTRL6_SEC2_DOM7_SHIFT  (9)
#define SRAMROM_SEC_CTRL6_SEC3_DOM4_SHIFT  (16)
#define SRAMROM_SEC_CTRL6_SEC3_DOM5_SHIFT  (19)
#define SRAMROM_SEC_CTRL6_SEC3_DOM6_SHIFT  (22)
#define SRAMROM_SEC_CTRL6_SEC3_DOM7_SHIFT  (25)

#define SRAMROM_SEC_CTRL_SEC0_DOM0_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC0_DOM0_SHIFT)
#define SRAMROM_SEC_CTRL_SEC0_DOM1_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC0_DOM1_SHIFT)
#define SRAMROM_SEC_CTRL_SEC0_DOM2_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC0_DOM2_SHIFT)
#define SRAMROM_SEC_CTRL_SEC0_DOM3_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC0_DOM3_SHIFT)
#define SRAMROM_SEC_CTRL_SEC1_DOM0_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC1_DOM0_SHIFT)
#define SRAMROM_SEC_CTRL_SEC1_DOM1_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC1_DOM1_SHIFT)
#define SRAMROM_SEC_CTRL_SEC1_DOM2_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC1_DOM2_SHIFT)
#define SRAMROM_SEC_CTRL_SEC1_DOM3_MASK   (0x7 << SRAMROM_SEC_CTRL_SEC1_DOM3_SHIFT)

#define SRAMROM_SEC_CTRL2_SEC0_DOM4_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC0_DOM4_SHIFT)
#define SRAMROM_SEC_CTRL2_SEC0_DOM5_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC0_DOM5_SHIFT)
#define SRAMROM_SEC_CTRL2_SEC0_DOM6_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC0_DOM6_SHIFT)
#define SRAMROM_SEC_CTRL2_SEC0_DOM7_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC0_DOM7_SHIFT)
#define SRAMROM_SEC_CTRL2_SEC1_DOM4_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC1_DOM4_SHIFT)
#define SRAMROM_SEC_CTRL2_SEC1_DOM5_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC1_DOM5_SHIFT)
#define SRAMROM_SEC_CTRL2_SEC1_DOM6_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC1_DOM6_SHIFT)
#define SRAMROM_SEC_CTRL2_SEC1_DOM7_MASK  (0x7 << SRAMROM_SEC_CTRL2_SEC1_DOM7_SHIFT)

#define SRAMROM_SEC_CTRL5_SEC2_DOM0_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC2_DOM0_SHIFT)
#define SRAMROM_SEC_CTRL5_SEC2_DOM1_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC2_DOM1_SHIFT)
#define SRAMROM_SEC_CTRL5_SEC2_DOM2_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC2_DOM2_SHIFT)
#define SRAMROM_SEC_CTRL5_SEC2_DOM3_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC2_DOM3_SHIFT)
#define SRAMROM_SEC_CTRL5_SEC3_DOM0_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC3_DOM0_SHIFT)
#define SRAMROM_SEC_CTRL5_SEC3_DOM1_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC3_DOM1_SHIFT)
#define SRAMROM_SEC_CTRL5_SEC3_DOM2_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC3_DOM2_SHIFT)
#define SRAMROM_SEC_CTRL5_SEC3_DOM3_MASK  (0x7 << SRAMROM_SEC_CTRL5_SEC3_DOM3_SHIFT)

#define SRAMROM_SEC_CTRL6_SEC2_DOM4_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC2_DOM4_SHIFT)
#define SRAMROM_SEC_CTRL6_SEC2_DOM5_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC2_DOM5_SHIFT)
#define SRAMROM_SEC_CTRL6_SEC2_DOM6_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC2_DOM6_SHIFT)
#define SRAMROM_SEC_CTRL6_SEC2_DOM7_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC2_DOM7_SHIFT)
#define SRAMROM_SEC_CTRL6_SEC3_DOM4_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC3_DOM4_SHIFT)
#define SRAMROM_SEC_CTRL6_SEC3_DOM5_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC3_DOM5_SHIFT)
#define SRAMROM_SEC_CTRL6_SEC3_DOM6_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC3_DOM6_SHIFT)
#define SRAMROM_SEC_CTRL6_SEC3_DOM7_MASK  (0x7 << SRAMROM_SEC_CTRL6_SEC3_DOM7_SHIFT)

#define PERMIT_S_RW_NS_RW       (0x0)
#define PERMIT_S_RW_NS_BLOCK    (0x1)
#define PERMIT_S_RW_NS_RO       (0x2)
#define PERMIT_S_RW_NS_WO       (0x3)
#define PERMIT_S_RO_NS_RO       (0x4)
#define PERMIT_S_BLOCK_NS_BLOCK (0x5)

#define DISABLE_SEC_SEC1_PROTECTION (0x0)
#define ENABLE_SEC_SEC1_PROTECTION  (0x1)
